1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming 3D semiconductor devices, such as FinFET devices, wherein different FinFET devices have different fin heights, and to an integrated circuit product that contains such FinFET devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive currents than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
One process flow that is typically performed to form FinFET devices involves forming a plurality of trenches in the substrate to define the areas where STI regions will be formed and to define the initial structure of the fins. These trenches are typically formed in the substrate during the same process operation for processing simplicity. The trenches have a target depth that is sufficient for the needed fin height and deep enough to allow formation of an effective STI region. After the trenches are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the trenches. Thereafter, a chemical mechanical polishing (CMP) process is then performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Thereafter, an etch-back process is performed to recess the layer of insulating material between the fins and thereby expose the upper portions of the fins, which corresponds to the final fin height of the fins.
Given the way that fins are typically formed, a conventional FinFET device has a fixed fin height, i.e., all of the fins have the same height. Thus, the total channel width of a multiple fin FinFET device is equal to the number of fins (“X”) times the channel width provided by each fin, i.e., each fin provides a channel length equal to two times (2×) the vertical fin-height plus the width of the top surface of the fin. That is, the total channel width of a multiple fin device is fixed by the fin height and number of fins. Importantly, using traditional manufacturing techniques, a FinFET device with multiple fins, e.g., a two-fin device, cannot be manufactured such that the total channel width of the device is equal to, for example, 1.5 times the total height of the two fins in the two-fin device. This lack of flexibility in manufacturing FinFET devices provides designers with less flexibility than would otherwise be desired in designing complex integrated circuits.
In designing digital circuits, one parameter that is very important is the desired drive current produced by individual transistors (FETs and/or FinFETs) and the overall drive current needed or produced by a given circuit arrangement. In circuits involving planar FETs, device designers can produce FETs that generate a virtually desired fractional level of drive current. That is, for planar FETs, the drive current of the FET may be readily adjusted to virtually any value by simply changing the gate width of the planar FET. For example, if a designer desires a FET with ½ strength drive current, then the gate width of a planar FET with an integer drive strength of 1 is simply reduced by half. Similarly, if twice the drive strength of a planar FET is required, then the gate width of the FET is doubled. Of course, increasing the gate width of a planar FET device consumes more plot space, but the ability to produce planar FETs with desired fractional drive currents gives device designers great flexibility in designing integrated circuits. Many digital and analog circuits are based upon designs that involve fractional drive current strengths. However, as discussed above, with FinFETs, the channel width is fixed by the height of the fin.
Additionally, for some integrated circuit products, it is necessary that one FinFET based device produce more drive current than another FinFET device in the same circuit. For example, in an SRAM product, there is an optimized drive current ratio between the so-called pass-gate transistor, pull-up transistor and pull-down transistor. In practical terms, given the fixed fin height of FinFET devices, the pass-gate transistor must be physically different in plot-space size than the pull-up transistor to get the desired difference in drive current, e.g., the transistors consume different amounts of plot space on the substrate. Unfortunately, this size differential can adversely affect patterning operations as etching processes may be affected by locally varying densities in circuit features. Such variations in the resulting device structures can adversely affect device performance.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time in an effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices.
The present disclosure is directed to various methods of forming 3D semiconductor devices, such as FinFET devices, wherein different FinFET devices have different fin heights, and to an integrated circuit product that contains such FinFET devices that may solve or reduce one or more of the problems identified above.